Staff Hardware Board Design Engineer

About the role

Gateworth Group is supporting a fast-growing AI company in Dubai by hiring a Staff Hardware Board Design Engineer to take full ownership of board-level design for next-generation platforms. The role suits a hands-on engineer who has delivered high-speed digital boards from concept through production and led first-silicon bring-up on the bench. It is not a program or system management role, but deep, practical engineering with responsibility for whether new silicon powers up, margins and ships.

Key responsibilities

• Lead board-level architecture and schematic ownership for accelerator cards, modules and test platforms.
• Design evaluation and bring-up hardware for new ASICs/SoCs, including power rails, sensing, clocking, access ports and instrumentation points.
• Define stackup, materials, impedance targets and routing constraints for PCIe Gen4/5/6, DDR5, LPDDR5, GDDR and 25G+ SerDes interfaces.
• Architect high-current PDNs and multi-phase VRMs at hundreds of amps, including sequencing, PMBus telemetry and decoupling strategy.
• Drive first-silicon bring-up: power-on, characterization, margining and cross-functional debug across hardware, firmware and silicon.
• Use lab instrumentation such as oscilloscopes, high-bandwidth probes, VNAs, BERTs, protocol analyzers, power analyzers and thermal tools.
• Apply Python for lab automation, data capture and measurement workflows.
• Oversee DFM/DFT/DFA, prototype builds, ECOs, BOM control and vendor engagement through fabrication and assembly.
• Act as design authority in reviews, producing documentation, test plans and alignment across silicon, firmware, mechanical and manufacturing teams.

Required profile

• 10+ years of board-level high-speed digital design experience.
• Schematic and architecture ownership in the last 3 years in Allegro System Capture, OrCAD/Altium or Xpedition.
• One platform personally owned end-to-end from concept through volume production.
• One first-silicon bring-up where you designed the board powering up a new ASIC/SoC.
• Experience defining stackup and routing constraints for PCIe Gen4+, DDR5, LPDDR5, GDDR or 25G+ SerDes.
• Strong PDN and multi-phase VRM design at high current, including PMBus and sequencing.
• Solid understanding of DFM, DFT, DFA and manufacturing processes.

Not suitable: program or system leads managing ODM-executed designs; engineers whose hands-on design ended before around 2020; sustaining, validation or test engineers without board architecture ownership.

Applications are submitted through the apply link; further questions can be sent to the recruiter by quoting the reference #15131.