High-Speed PCB Layout Engineer

About the role

We are a fast‑growing AI hardware company seeking a High‑Speed PCB Layout Engineer to turn schematics and constraints into dense, manufacturable multi‑layer boards for AI accelerator platforms and silicon test fixtures. The role is on‑site in Dubai and focuses on high‑frequency signal routing, power delivery, and stack‑up definition.

Key responsibilities

• Own end‑to‑end multi‑layer PCB layout for accelerator cards, modules, system boards, and test fixtures.
• Execute escape routing for fine‑pitch BGA packages and route multi‑gigabit channels such as PCIe Gen6, GDDR7, and 400 G/800 G Ethernet.
• Define and negotiate layer stack‑ups, dielectric materials, impedance targets, and loss budgets with fabricators.
• Build and maintain constraint sets in Cadence Allegro Constraint Manager, handling differential pair tuning, delay/skew matching, and crosstalk control.
• Design high‑current power distribution networks, including plane partitioning, copper weight, thermal via strategy, and decoupling placement.
• Iterate with signal and power integrity engineers using simulation results to meet electrical margins.
• Lead DFM, DFA, and DFT reviews with fab and assembly vendors.

Required profile

• Proven experience in high‑speed PCB layout for complex, high‑density boards.
• Strong knowledge of signal and power integrity principles.
• Ability to collaborate with design, silicon, and manufacturing teams.

Required skills

• Cadence Allegro (Constraint Manager)
• HDI design, via‑in‑pad, VIPPO, blind and buried vias, backdrilling
• PCIe Gen6, GDDR7, 400 G/800 G Ethernet routing
• Stack‑up definition, impedance control, loss budgeting
• Signal integrity and power integrity analysis
• DFM/DFA/DFT review processes

What we offer

• Dynamic, fast‑growing environment at the forefront of AI hardware innovation.
• Opportunities to impact cutting‑edge accelerator designs.
• Competitive compensation and benefits package.